Application Notes

Quartz Crystal Notes
A quartz crystal resonates when an

electrical potential is applied to its surfaces, causing mechanical deformation(vibration). This phenomenon is called the piezoelectric effect. When metal electrodes are placed on both sides of a crystal plate, the piezoelectric response between the electrodes can be

expressed as the equivalent electrical parameters shown in Figure 1.

Mode of Oscillation
The Oscillation Mode for AT cut quartz crystals is at the fundamental mode or and odd frequency harmonic of the fundamental  frequency. Standard 3rd overtone mode, followed by 5th, 7th ,9th, etc.

Frequency Tolerance @25℃
Frequency Tolerance is the minimum and the maximum frequency deviation allowed from the Target Frequency @25. This deviation is usually specified in ±ppm ( parts per million ).

Frequency Stability
Frequency Stability is the amount of frequency deviation that will occur over the Operating Temperature Range with respect to the frequency @25.This deviation is often associated with other specified operating conditions such as Load Capacitance and Drive Level.. Temperature is a major influence on crystal frequency.

Equivalent Series Resistance(ESR or R1)
ESR is the resistance (in Ohms) that the crystal exhibits at

resonance. Equation (1)

Shunt Capacitance

Shunt capacitance (C0) is the capacitance between the crystal terminals. It varies with package, usually it is smaller in SMD (4pF typical) and is 6pF in leaded crystals.

Load Capacitance
Crystals can be calibrated by the manufacturer at either fr, where they appear resistive (or fs which is very close to fr),or for resonance with a  capacitive load, where of course they must appear inductive. The latter condition is called load –resonant and is represented in general terms by the symbol fL or ,more specifically, the symbol f 30 would , for example , represent the frequency at which the crystal is at resonance with a 30 pF capacitor.

Motional Capacitance (C1)
Motional Capacitance (C1) is a parameter largely controlled by the design of the electrode size and shape. When C1 is specified, it  should be specified with a maximum and a minimum value in pf of fF. C1 has physical design limitations due to constraints in quartz blank size, mode of operation and nominal frequency. L1 is usually not specified because it is virtually specified by C1 due to the absolute relationship shown in Equation 2.

Equation ( 2 )

Storage Temperature Range
The Storage Temperature Range is the absolute limits of temperature to which the device will be exposed in a non-oscillation state.

Pullability and Change of Load Capacitance

change as a function of load capacitance CL in a parallel resonant crystal. Pullability is a function of shunt capacitance C0, motional capacitance C1, and size of crystal. When a

crystal is operating at parallel resonance (Fs<Fr<Fa),it looks inductive in the circuit. As the reactance changes, the frequency changes correspondingly, thus change the pullability of the crystal.See Equation (3) .The same crystal with frequency at 3rd-overtone mode will have much less pulling because its ’motional capacitance C1` is approximately 1/9 of C1 at fundamental.

Equation (3)

Unwanted resonances usually above the operating mode, specified in dB max. or number of times of ESR. Frequency range must be specified. In oscillator applications, it is necessary to control unwanted modes as lower as
possible to prevent circuit oscillating in the “spurious mode ”.See Figure 3. The design of large electrodes on crystal to produce large pulling is a common cause of prompting spurious. A resistance ration of 2:1 or minimum of 3db separation

is usually adequate.

Aging is the change in operating frequency over a certain

period of time .It is usually expressed as a maximum value in ppmper year. Typical crystal aging:±5ppm per year max..

DLD(Drive Level Dependency)
To change a crystal of drive level
that will change the frequency or resistance, the effect is called DLD Usually DLD is a ration between the largest resistance measured over a user defined power range ,and the resistance at the nominal power . DLD is a good measure of internal cleanliness of crystals.


Oscillator Notes
A crystal oscillator is a timing device that consists of a crystal and an oscillator circuit, providing an output waveform at a specific frequency. When a crystal is placed into an amplifier circuit(as shown in Figure 4 ),a small amount of energy is feedback to the crystal, which causes it to

vibrate. These vibrations act to stabilize the frequency of the oscillator circuit.

Supply Current(ICC)
The current flowing into Vcc terminal
with respect to ground. Typical supply current is measured without load.

Supply Voltage(VDC max)
The maximum voltage which can safely be applied to the VDC terminal with respect to ground .

 Symmetry ( Duty Cycle )
Symmetry is a measurement of the time that the output waveform is in a logic high state, expressed as a percentage (%) of the complete cycle. A typical symmetry tolerance is 40/60%. Tight symmetry is considered to be 45/55%.

Rise / Fall Time
Rise Time is a measure of the

transition time from a “Logic 0” to a “Logic 1” level.Fall Time is a measure of the transition time from a “Logic 1” to a “Logic 0” level. Both Rise and Fall Time are typically specified as a maximum transition time in ns. Typical rise and fall time for CMOS 4000 series is 30ns, HCMOS is 6ns, and for HCMOS/TTL compatible) is 3 ns max..( See Figure 5 )

Output load
Output Load is the maximum load an

oscillator can drive. It is specified in terms of number

of gates or type of load circuit. An HCMOS load is usually specified as a capacitive load in pF. TTL loads are specified as a number of TTL gates.

Start-up time
Start-up time is the delay time between the
oscillation starts from noise until it reaches its full output amplitude when power is applied. The start-up time varies from microseconds to milliseconds depending on frequency, ASIC speed and logic. See figure 6.

VCXO ( Voltage Controlled Crystal Oscillator )

A VCXO is an oscillator that allows the user to vary the Output Frequency by varying a Control Voltage applied to pin 1.